This invention relates generally to the formation of circuit boards or cards or the like, and more particularly to the formation of circuit boards or cards having 2 signal planes and one power plane (2S/1P) wherein the power plane is sandwiched between two layers of photopatternable dielectric material and on which layers of circuitry for the signal planes is disposed.
In certain conventional circuit board configurations, the circuit board cross-sectionxe2x80x94includes non-photopatternable dielectric, such as FR4 which is epoxy impregnated fiberglass, and one or more layers of copper. Vias and plated through holes are mechanically or laser drilled in the dielectric material. This requires precise alignment drilling with each hole being drilled idefinately and sequentially. Moreover, in some instances it is necessary that there be an isolation border around the edge of the card or board to prevent the power plane from being exposed at the edge. Isolation borders are also created within a card or board to allow separate voltage areas on the same plane. Isolation borders are created by etching away the copper, which exposes the FR4 material therebelow. The exposed FR4 material isolates two adjacent areas of copper, which by design should not be in contact with each other. The isolation border is also used around the edge of the board to prevent exposed copper on the edges from abutting together in the card or board profile operation. The same technique is used to display text on the board, such as part numbers, etc.
While photoimageable material has been used on one side of a metal substrate, various processing difficulties are encountered when using photoimageable material to form a 2S/1P board, with the photoimageable material on both sides of the metal power plane. In a process that sandwiches a preformed metal power plane with photoimageable dielectric polymers as the dielectric material on which circuit traces are to be formed, isolation borders cannot be formed in the same way as with the non-photopatternable FR4. If the same process were used after the copper is etched away, the parts of the panel would be isolated and would literally fall apart since there is no remaining material to hold them together.
It is therefore a principal object of the present invention to provide a process in which layers of photoimageable dielectric material are used on opposite sides of a metal layer forming a power plane and on which circuit traces are formed and in which vias and plated through holes are formed. In one aspect a technique is provided wherein an isolation border can be formed in the power plane without the panel falling apart.
According to the present invention, a method of forming a printed circuit board or circuit card is provided wherein there is metal layer which serves as a power plane sandwiched between a pair of photoimageable dielectric layers, and wherein photoformed metal filled vias and photoformed plated through holes are formed in the photopatternable material, and signal circuitry is formed on the surfaces of each of the dielectric materials and connected to the vias and plated through holes. In one embodiment, a border around the board or card is provided wherein said metal layer terminates a distance spaced from the edge of one of the dielectric layers. A border can also be used within a card or board to isolate separate voltages on the same plane. The method includes the steps of providing a layer of metal preferably copper foil with clearance holes. A first layer of photoimageable dielectric curable material is disposed on one side of the foil, and a second layer of photoimageable curable dielectric material is disposed on the other side of said layer of material. Preferably, the photoimageable dielectric material is an epoxy-based resin.
Both the first and second layers of the curable photoimageable material are photopatterned in a pre-selected pattern on each side. (If a border is to be formed, the first layer of photoimageable material includes a border pattern, and the pattern on the second layer of photoimageable material does not include the border pattern.) The patterns are developed on the first and second layers of the photoimageable material to reveal the metal layer through vias and in the case of a border to reveal the metal at the border in the developed patterns. At the clearance holes in the metal layer, through holes have been developed where holes were patterned in both dielectric layers Thereafter, the surface of each of the photoimageable material, vias and through holes are metalized by the use of photolithographic technique and preferably through additive copper plating. If a border is present, the metal surrounding the borders revealed through the first layer is etched to thereby provide a substrate which has an edge defined by the second layer of photoimageable material extending beyond the edge of the metal layer. This etching is preferably done by protecting the remainder of the circuitry by the use of photoresist and utilizing photolithographic techniques. When such technique is used, the photoresist is thereafter removed, thereby leaving a circuit board or card having metalization on both sides, vias extending from both sides to the metal layer in the center, plated through holes connecting the two outer circuitized metal layers, and in the case of forming a board with the metal removed to form a border supported by one of the patternable dielectric materials which remain undeveloped.